(a) Field of the Invention
The present invention relates to a data latch circuit and, more particularly, to a data latch circuit capable of accurately latching a data signal transferred in a semiconductor device.
(b) Description of the Related Art
With the improvement for finer patterns and high integration in semiconductor device as well as the improvement for a larger capacity therein, some of semiconductor products will have a larger chip area. In order for implementing a larger chip area along with a higher operational-speed in a semiconductor device, improvement for the signal transmission function is especially required for the semiconductor elements without generating an error signal between any locations in the larger chip area of the semiconductor device.
In a semiconductor memory device, for example, a latch circuit is generally used therein as a functional element for effecting accurate take-in or latch of data. The latch circuit is provided in the semiconductor memory device, for example, at the location of an output port or an input port of a digit line for latching the data read out from a memory cell. The latch circuit generally maintains the data latched therein accurately as it is for a specified period.
FIG. 1 shows a schematic configuration of a conventional latch circuit in a semiconductor memory device for latching data delivered from a pair of data transmission lines, such as a pair of complementary digit lines or output lines from a sense amplifier. In this text, the data transmission lines, the digit lines and other data lines having a similar function are collectively referred to as digit lines hereinafter. The latch circuit includes a transfer gate section implemented by a pair of MOSFETs including a pMOSFET 11 and an nMOSFET 12, and a flipflop section implemented by a pair of inverters 16 and 17 wherein each of the outputs of the inverters 16 and 17 is connected to the input of the other of the inverters 16 and 17. The flipflop section may be referred to as a latch section because the latch section functions in fact for take-in of the data, whereas the transfer gate section opens or closes the gate for inputs of the latch section.
The transfer gate section 11 and 12 is disposed between a pair of digit lines 13 and 14 and the flipflop section 16 and 17. The digit lines 13 and 14 receive a pair of complementary signals having opposite phases. The flipflop section functions for latching and holding the data as well as transferring the latched data to another succeeding gate not shown in the figure. MOSFETs 11 and 12 of the transfer gate section are controlled by a latch timing control signal 15 for controlling the latch timing of the latch circuit.
FIG. 2 illustrate a latch timing in the latch circuit of FIG. 1, wherein periods T1 to T3 of a single data transmission cycle are shown in relation to the potential change on the digit lines 13 and 14 whereas periods T4 to T6 are shown in relation to the stage of the transfer gate section. During periods T1 and T3, digit lines 13 and 14 are equalized for the potentials thereof, and during period T2, the data signal constituting complementary signals are transferred to the digit lines from a preceding gate. The transfer gate section is closed during period T4, opened during period T5 and closed again during period T6. The periods T4 to T6 are controlled by the latch timing control signal 15, which is supplied from a CPU which controls the transfer gate section 11 and 12.
The latch circuit of FIG. 1 has a latched state wherein the transfer gate section is closed during the equalizing period T1, a through state wherein the transfer gate section is opened during period T5, which starts before the start of period T2, for latching the data by the latch section, and another latched state wherein the transfer gate section is closed again before the end of period T5 which resides within period T2.
It is important to determine the timing of the data latch by opening the transfer gate section 11 and 12. If the data is latched at the timing at which the amplitudes of data waveforms 22 and 23 shown in FIG. 2 are small, the latch section cannot correctly determine the data, resulting in transmission of an error signal. Particularly, in the case of a high-speed semiconductor device, since the time length of period T2 therein is short, the optimum timing of the data latch is generally difficult to determine.
Especially in the case of a semiconductor device having a large chip area, the difficulty in determining the optimum timing increases further. Referring to FIG. 3 exemplary showing a semiconductor memory device having a large chip size, the memory device includes an array of memory cell areas 31 including specific cell areas 31a and 31b, a plurality of data transmission lines including data transmission lines 32a and 32b corresponding to cell areas 31a and 31b, respectively, and a latch circuit 33 for latching data read out the cell areas 31 through the data transmission lines. The latch circuit 33 receives a latch timing control signal 34 from a control section 35.
In the situation as described above, the difference between the time instants at which data are transmitted from the cell areas 31 and 31b to the latch circuit 33 is caused by the difference in lengths of the data transmission lines 32a and 32b. If the timing for the transfer gate section in the latch circuit 33 is determined by the control section 35 at an optimum timing for the specified cell area 31a, for example, the latch of data supplied from the cell area 31b is performed before an optimum timing for the cell area 31b, thereby raising a possibility of an error signal transmission due to the difference in length of the transmission line.
In short, the difference in the transmission line for the data signal and the control signal together with the higher-speed transmission in the semiconductor device causes an error signal transmission in a semiconductor device.